Digital Logic Design Lab.（101學年度第2學期 數位邏輯設計實習）
Course Announcements（公告事項 ）
Course Syllabus（課程綱要 ）
Course Syllabus（in PPT Format; Used in the class for introduction）
LabReportTemplateinPDF LabReportTemplateinWORD（Due: May 17, 2013）
除一般電阻、電容外，下列裝備均需裝載於收納盒中繳回（電子零件以夾鍊袋收納）：
可變電阻x 4個
七段顯示器x 1個
IC NE555, 4011, 4584, TL082, PEEL18CV8 各x 1個
DE0實驗模組x 1個
麵包板x 1塊
電源線（紅）x 2條（香蕉頭對鱷魚夾）
電源線（黑）x 1條（香蕉頭對鱷魚夾）
示波器訊號線x 1條（BNC對鱷魚夾）
Lecture Notes
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PART I: EDA Tools
EDA Tools Training Material Download
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PART II: PLD (Programmable Logic Device) and Oscillation Circuits
※ Introduction to oscillation circuits
Mainly focused on square wave generator, however the Wien Bridge oscillator will also be introduced here for its importance.
Oscillation Circuits (in PDF format)
Oscillation Circuits (in SCH format)
※實驗注意事項：
方波震盪電路部分：
1. 4584-Based RC震盪電路：請量測訊號變形前之最高震盪頻率，請觀察並記錄電容電壓之波形
2. NAND Gate-Based可控制震盪電路：請將震盪頻率調整至38KHz，請觀察並記錄電容電壓之波形（注意電壓跳升的現象）
3. NE555不穩態多諧震盪電路：請紀錄該電路是否為對稱方波、最高震盪頻率為何，請觀察並記錄電容電壓之波形（是否對稱）
正弦波震盪電路部分：
1. Wien Bridge震盪電路：請紀錄震盪頻率為何、電壓峰值為何
請務必確認已完成上述各項要求並請記錄實驗結果以利撰寫實驗報告時使用！
簡易移難/障礙排除：
1. 電源供應器使用與設定（同時需正負電源時可選擇Series模式，在此模式下兩個通道一正一負且連動）
2. 示波器的頻率自動量測：按下Measure後再選通道編號即可選擇需自動量測之參數
3. 雜訊過大時請於電源接點加上Bypass電容；亦即旁路電容，加上10uF電解質電容即可大幅改善雜訊現象
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※ Introduction to PLD（PEEL18CV8）
PEEL18CV8 (Programmable Logic Device；PLD PEEL18CV8)
Tools for PEEL18CV8：PLDTools (Assembler for PEEL Components and Some Examples)
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PART III: CPLD (Complex PLD) / FPGA (Field Programmable Gate Array)
※ Introduction to ALTERA-DE0 module
DE0 User Manual Getting Start with ALTERA DE0 board
※ Courtesy of Prof. Yuan-Hao Chang for sharing his great and excellent teaching materials on the labs of ALTERA-DE0 platform.
Lecture-FPGA-1: ALTERA-DE0 FPGA development board and Quartus II 9.1 design software - Two-partition format；Six-partition format
Lecture-FPGA-2: Introduction to VHDL - Two-partition format；Six-partition format
Lecture-FPGA-3: Combinational Logic Functions - Two-partition format；Six-partition format
Lecture-FPGA-4: Combinational Logic Functions-2 - Two-partition format；Six-partition format
Lecture-FPGA-5: SequentialLogic-Latch - Two-partition format；Six-partition format
Lecture-FPGA-6: SequentialLogic-FlipFlop - Two-partition format；Six-partition format
Lecture-FPGA-7: ShiftRegisters - Two-partition format；Six-partition format
Lecture-FPGA-8:
StateMachine -
Two-partition format；Six-partition
format